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ics854s057bgi revision a march 29, 2010 1 ?2010 integrated device technology, inc. data sheet 4:1 or 2:1 lvds clock multiplexer with internal input termination ICS854S057BI 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 npclk1 vt1 pclk1 sel0 sel1 npclk0 vt0 pclk0 v dd gnd v dd pclk3 vt3 npclk3 q nq pclk2 vt2 npclk2 gnd general description the ICS854S057BI is a 4:1 or 2:1 lvds clock multiplexer which can operate up to 2ghz. the pclk, npclk pairs can accept mo st standard differential input levels. internal termination is provided on each differential input pair. the ICS854S057BI operates using a 2.5v supply voltage. the fully differential architecture and low propagation delay make it ideal for use in high speed multiplexing applications. the select pins have internal pulldown resistors. leaving one input unconnected (pulled to logic low by the internal resistor) will transform the device into a 2:1 multiplexer. the sel1 pin is the most significant bi t and the binary number applied to the select pins will select the sa me numbered data input (i.e., 00 selects pclk0, npclk0). features ? high speed differential multiplexer. the device can be configured as either a 4:1 or 2:1 multiplexer ? one lvds output pair ? four selectable pclk, npclk inputs with internal termination ? pclkx, npclkx pairs can accept the following differential input levels: lvpecl, lvds, cml, sstl ? maximum output frequency: >2ghz ? part-to-part skew: 200ps (maximum) ? propagation delay: 800ps (maximum) ? additive phase jitter, rms: 0.065ps (typical) ? full 2.5v power supply ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package hiperclocks? ic s 0 0 0 1 1 0 1 1 q nq vt0 pclk0 npclk0 sel1 sel0 50 50 vt1 pclk1 npclk1 50 50 vt2 pclk2 npclk2 50 50 vt3 pclk3 npclk3 50 50 pulldown pulldown pin assignment ICS854S057BI 20-lead tssop 4.4mm x 6.5mm x 0.925mm package body g package top view block diagram
ICS854S057BI data sheet 4:1, or 2:1 lvds clock multiplexer w/internal input termination ics854s057bgi revision a march 29, 2010 2 ?2010 integrated device technology, inc. table 1. pin descriptions note: pulldown refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics table 3. control input function table number name type description 1, 20 v dd power power supply pins. 2 pclk0 input non-inverting lvpecl differential clock input. r t = 50 ? termination to vt0. 3 vt0 input termination input. for lvds input, leave floating. r t = 50 ? termination to vt0. 4 npclk0 input inverting lvpecl differential clock input. r t = 50 ? termination to vt0. 5, 6 sel1, sel0 input pulldown clock select inputs. lvcmos/lvttl interface levels. 7 pclk1 input non-inverting lvpecl differential clock input. r t = 50 ? termination to vt1. 8 vt1 input termination input. for lvds input, leave floating. r t = 50 ? termination to vt1. 9 npclk1 input inverting lvpecl differential clock input. r t = 50 ? termination to vt1. 10, 11 gnd power power supply ground. 12 npclk2 input inverting lvpec l differential clock input. r t = 50 ? termination to vt2. 13 vt2 input termination input. for lvds input, leave floating. r t = 50 ? termination to vt2. 14 pclk2 input non-inverting lvpecl differential clock input. r t = 50 ? termination to vt2. 15, 16 nq, q output differential outpu t pair. lvds interface levels. 17 npclk3 input inverting lvpec l differential clock input. r t = 50 ? termination to vt3. 18 vt3 input termination input. for lvds input, leave floating. r t = 50 ? termination to vt3. 19 pclk3 input non-inverting lvpecl differential clock input. r t = 50 ? termination to vt3. symbol parameter test conditi ons minimum typical maximum units c in input capacitance 2pf r pulldown input pulldown resistor 50 k ? r t input termination resistor 40 50 60 ? inputs outputs sel1 sel0 pclkx, npclkx 0 0 pclk0, npclk0 0 1 pclk1, npclk1 1 0 pclk2, npclk2 1 1 pclk3, npclk3
ICS854S057BI data sheet 4:1, or 2:1 lvds clock multiplexer w/internal input termination ics854s057bgi revision a march 29, 2010 3 ?2010 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. lvds power supply dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c table 4c. lvpecl differen tial dc char acteristics, v dd = 2.5v 5%, t a = -40c to 85c note 1: guaranteed by design. note 2: v il should not be less than -0.3v. note 3: common mode input voltage is defined as v ih . item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuos current surge current 10ma 15ma input current, pclk, npclk 50ma v t current, i vt 100ma package thermal impedance, ja 92.1c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 2.375 2.5 2.625 v i dd power supply current 50 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v dd = 2.5v 1.7 v dd + 0.3 v v il input low voltage v dd = 2.5v -0.3 0.7 v i ih input high current sel0, sel1 v dd = v in = 2.625v 150 a i il input low current sel0, sel1 v dd = 2.625v, v in = 0v -10 a symbol parameter test conditions minimum typical maximum units i in absolute input current; note 1 v dd = v in = 2.625v 35 ma v pp peak-to-peak voltage; note 2 0.15 1.2 v v cmr common mode input voltage; note 2, 3 gnd + 1.2 v dd v
ICS854S057BI data sheet 4:1, or 2:1 lvds clock multiplexer w/internal input termination ics854s057bgi revision a march 29, 2010 4 ?2010 integrated device technology, inc. table 4d. lvds dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c table 5. ac characteristics, v dd = 2.5v 5%, t a = -40c to 85c note: all parameters measured at ? 1.9ghz unless noted otherwise. note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between different devices operating at the same supply voltage, same frequency and with equal load cond itions. using the same type of inputs on each device, the out put is measured at the differential cross point. note 3: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 225 325 425 mv ? v od v od magnitude change 4 35 mv v os offset voltage 1.125 1.25 1.375 v ? v os v os magnitude change 5 25 mv symbol parameter test conditio ns minimum typical maximum units f max output frequency >2 ghz t pd propagation delay; note 1 300 800 ps tsk (pp) part-to-part skew; note 2, 3 200 ps tsk (i) input skew 40 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section 622.08mhz, integration range: 12khz ? 20mhz 0.065 ps t r / t f output rise/fall time 20% to 80% 50 250 ps odc output duty cycle 700mhz 49 51 % ? 1.1ghz 47 53 % ? 2ghz 43 57 % mux isolation mux isolation ? = 500mhz -65 dbm
ICS854S057BI data sheet 4:1, or 2:1 lvds clock multiplexer w/internal input termination ics854s057bgi revision a march 29, 2010 5 ?2010 integrated device technology, inc. additive phase jitter the spectral purity in a band at a sp ecific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from th e fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is ma thematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. the source generator "rohde & schwarz sma100a low noise signal generator as external input to an agilent 8133a 3ghz pulse generator". ssb phase noise dbc/hz offset from carr ier frequency (hz)
ICS854S057BI data sheet 4:1, or 2:1 lvds clock multiplexer w/internal input termination ics854s057bgi revision a march 29, 2010 6 ?2010 integrated device technology, inc. parameter measureme nt information lvds output load ac test circuit mux isolation input skew differential input level part-to-part skew propagation delay scope q nq lvds 2.5v5% power supply +? float gnd v dd amplitude (db) a0 spectrum of output signal q mux _isol = a0 ? a1 (fundamental) frequency ? mux selects static input mux selects active input clock signal a1 t pd2 t pd1 tsk(i) = |t pd1 - t pd2 | tsk(i) npclkx pclkx npclky pclky nq q v dd npclk[0:3] pclk[0:3] gnd v cmr cross points v pp t sk(pp) part 1 part 2 q nq q nq t pd nq q pclk[0:3] npclk[0:3]
ICS854S057BI data sheet 4:1, or 2:1 lvds clock multiplexer w/internal input termination ics854s057bgi revision a march 29, 2010 7 ?2010 integrated device technology, inc. parameter measurement in formation, continued output rise/fall time differential output voltage setup output duty cycle/pulse width/period offset voltage setup 20% 80% 80% 20% t r t f v od q nq ? ? ? 100 out out lvds dc input v od / ? v od v dd t pw t period t pw t period odc = x 100% q nq out out lvds dc input ? ? ? v os / ? v os v dd
ICS854S057BI data sheet 4:1, or 2:1 lvds clock multiplexer w/internal input termination ics854s057bgi revision a march 29, 2010 8 ?2010 integrated device technology, inc. application information recommendations for unused input pins inputs: lvcmos control pins all control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. 2.5v differential i nput with built-in 50 ? termination unused input handling to prevent oscillation and to reduce noise, it is recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in figure 1. figure 1. unused input handling receive r with built-in 50 ? pclk npclk vt 2.5v 2.5v r2 680 r1 680
ICS854S057BI data sheet 4:1, or 2:1 lvds clock multiplexer w/internal input termination ics854s057bgi revision a march 29, 2010 9 ?2010 integrated device technology, inc. 2.5v lvpecl input with built-in 50 ? termination interface the pclk /npclk with built-in 50 ? terminations accept lvds, lvpecl, cml, sstl and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the pclk /npclk with built-in 50 ? termination input driven by the most common driver types. the input interfaces suggested here are exampl es only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 2a. pclk/npclk input with built-in 50 ? driven by an lvds driver figure 2c. pclk/npclk input with built-in 50 ? driven by a cml driver figure 2e. pclk/npclk input with built-in 50 ? driven by an sstl driver figure 2b. pclk/npclk input with built-in 50 ? driven by an lvpecl driver figure 2d. pclk/npclk input with built-in 50 ? driven by a cml driver with built-in 50 ? pullup pclk npclk vt receiver with built-in 50 ? lvds 3.3v or 2.5v 2.5v zo = 50 ? zo = 50 ? pclk npclk vt cml receive r with built-in 50 ? 2.5v 2.5v zo = 50 ? zo = 50 ? sstl r1 25 ? r2 25 ? pclk npclk vt receiver with built-in 50 ? 2.5v 2.5v zo = 50 ? zo = 50 ? pclk npclk vt receiver with built-in 50 ? r1 18 ? lvpecl 2.5v 2.5v zo = 50 ? zo = 50 ? cml - built-in 50 ? pull-up pclk npclk vt receiver with built-in 50 ? 2.5v 2.5v zo = 50 ? zo = 50 ?
ICS854S057BI data sheet 4:1, or 2:1 lvds clock multiplexer w/internal input termination ics854s057bgi revision a march 29, 2010 10 ?2010 integrated device technology, inc. lvds driver termination a general lvds interface is shown in figure 3. standard termination for lvds type output stru cture requires both a 100 ? parallel resistor at the receiver and a 100 ? differential transmission line environment. in order to avoid any transmission line reflection issues, the 100 ? resistor must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 3 can be used with either type of output structure. if using a non-standard termination, it is recommended to contact idt and conf irm if the output is a current source or a voltage source type structure. in addition, since these outputs are lvds compatible, the input receivers amplitude and common mode input range should be verified for compatibility with the output. figure 3. typical lvds driver termination schematic example figure 4 shows a schematic example of the ICS854S057BI. in this example, the pclk0/npclk0 and pclk1/npclk1 inputs are used. the decoupling capacitors should be physically located near the power pin. figure 4. ICS854S057BI lvds schematic example 100 ? ? + 100 ? differential transmission line lvds driver lvds receiver (u1,20) r2 680 zo = 50 zo = 50 vdd vdd vdd r3 680 zo = 50 zo = 50 r5 100 r1 680 u1 ics854057 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 vdd pclk0 vt0 npclk0 sel1 sel0 pclk1 vt1 npclk1 gnd gnd npclk2 vt2 pclk2 nq q vdd pclk3 vt3 npclk3 zo = 50 vdd vdd lvds + - r4 680 r6 18 zo = 50 vdd vdd vdd=2.5v lvds r1 1k lvpecl c2 0.1u (u1,1) r1 1k c1 0.1u
ICS854S057BI data sheet 4:1, or 2:1 lvds clock multiplexer w/internal input termination ics854s057bgi revision a march 29, 2010 11 ?2010 integrated device technology, inc. power considerations this section provides information on power dissipa tion and junction temperature for the ICS854S057BI. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS854S057BI is the sum of the core power plus the power dissipation in the load(s). the following is the power dissipation for v dd = 2.5v + 5% = 2.625v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipation in the load. power (core) max = v dd_max * i dd_max = 2.625v * 50ma = 131.25mw power dissipation for internal termination r t power (r t ) max = 4 * (v pp_max ) 2 / r t_min = (1.2v) 2 / 80 ? = 72mw total power_ max = 131.25mw + 72mw = 203.25mw 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and bond pad, and directly affects the reliabilit y of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 92.1c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.203w * 92.1c/w = 103.7c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 20 lead tssop, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 92.1c/w 86.5c/w 83.0c/w
ICS854S057BI data sheet 4:1, or 2:1 lvds clock multiplexer w/internal input termination ics854s057bgi revision a march 29, 2010 12 ?2010 integrated device technology, inc. reliability information table 7. ja vs. air flow table for a 20 lead tssop transistor count the transistor count for ICS854S057BI is: 375 this device is pin and function compatible and a suggested replacement for ics854057. package outline and package dimensions package outline - g suffix for 20 lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 92.1c/w 86.5c/w 83.0c/w all dimensions in millimeters symbol minimum maximum n 20 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ICS854S057BI data sheet 4:1, or 2:1 lvds clock multiplexer w/internal input termination ics854s057bgi revision a march 29, 2010 13 ?2010 integrated device technology, inc. ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 854s057bgilf ics54s057bil ?lead-free? 20 lead tssop tube -40 c to 85 c 854s057bgilft ics54s057bil ?lead-free? 20 lead tssop 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ICS854S057BI data sheet 4:1, or 2:1 lvds clock multiplexer w/internal input termination ics854s057bgi revision a march 29, 2010 14 ?2010 integrated device technology, inc. revision history sheet rev table page description of change date a 10 11 updated lvds output term ination application note. updated power dissipation calculatiion in power considerations application note. 3/26/10 a 11 corrected power dissipation calculation in th e power considerations application note. 3/29/10
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2010. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 ICS854S057BI data sheet 4:1, or 2:1 lvds clock multiplexer w/internal input termination

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